TVPC’19: IEEE International Workshop on Testing and Verification of Programmable Chips


Description


Programmable logic is an important achievement in the development of modern computer application technology. Compared with ASIC technology, programmable logic resources can be flexibly customized and reduced, with the advantages of high performance and low power consumption, and low cost and low risk. In the recent years, it has been widely used in high-reliability fields, consumer electronics, Internet of Things, and other intelligent field.

With the increasing complexity and large-scale increase of functions, the test sufficiency and test efficiency of programmable logic are very important, which will directly affect the safety and reliability of products. The International Workshop on Testing and Verification of Programmable Chips (TVPC) aims to provide a forum to bring together researchers, practitioners and experts to present and discuss their relevant results or experience in programmable logic chip verification, and the special emphasis will be put on the intersection of four fields.

Topics


FPGA/SOPC Testing and Validation

  • Accelerated verification and simulation
  • Modeling and Model assessment
  • IP verification
  • Debugging and Verification Visualization
  • Timing Analysis and Cross-Clock Domain Analysis
  • SOPC Software and hardware co-verification, Coverage analysis, testing methods and test case generation
  • FPGA/SOPC functional, physical, and comprehensive verification platform

FPGA/SOPC Formal Methods

  • Formal modeling and Model assessment
  • Formal coverage analysis
  • Property sanity check
  • SOPC/FPGA Formal verification
  • Equivalence analysis

FPGA/SOPC Safety and Reliability

  • Single particle effect and Total dose effect detection and prevention
  • SRAM/FLASH/Anti-fuse FPGA safety design
  • Safety fault injection and analysis
  • FPGA/SOPC Information security, side channel attack prevention
  • Safety and reliability Testing methods

New Trend in Testing

  • AI and intelligent IC verification
  • AI toward autonomous testing
  • Machine learning and its application in testing
  • Testing in emerging fields, including internet of things and automotive electronics
  • Functional safety in automotive electronics, ISO 26262

Submission


Authors are invited to submit original unpublished research papers as well as industrial practice papers. Simultaneous submissions to other conferences are not permitted. Detailed instructions for electronic paper submission, panel proposals, and review process can be found at https://qrs19.techconf.org/submission.

The length of a camera ready paper will be limited to eight pages, including the title of the paper, the name and affiliation of each author, a 150-word abstract, and up to 6 keywords. Shorter version papers (up to four pages) are also allowed.

Authors must follow the IEEE Computer Society Press Proceedings Author Guidelines to prepare their papers. At least one of the authors of each accepted paper is required to pay full registration fee and present the paper at the workshop. Arrangements are being made to publish selected accepted papers in reputable journals. Submissions must be in PDF format and uploaded to the conference submission site.

Submission

Program Chair


Jinbo Wang's avatar
Jinbo Wang China

Chinese Academy of Sciences, China

Program Committee


NameAffiliation 
Wanlin CaoArcas-techUSA
William HungCadence Design Systems IncUSA
Jun YuanArcas Micro ElectronicsChina